1. Field of the Invention
The present invention relates to inverters used in integrated circuit devices, and in particular to a high-speed, tristate inverter that minimizes switching delay.
2. Description of the Related Art
Tristate devices are well known in the art. In addition to receiving one or more input signals, tristate device receives an additional signal, typically called an output disable signal, for placing the output line of the device into a high impedance state. In a high impedance state, the output line functions as if it is not connected to the rest of the circuit. Thus, an output line of a tristate device typically provides one of three states: logic 0, logic 1, and high impedance.
FIG. 1 illustrates a known tristate inverter 100. Inverter 100 includes four transistors: p-type transistors 101 and 102, and n-type transistors 103 and 104. Referring to FIG. 1, the source S of transistor 101 is connected to a voltage source Vdd, typically 5 volts, whereas the drain D of transistor 101 is connected to the source S of transistor 102. The drain D of transistor 102 is connected to the drain D of transistor 103, as well as the output line 106. The source S of transistor 103 is connected to the drain D of transistor 104, whereas the source S of transistor 104 is connected to another voltage source Vss, typically ground. The gates G of transistors 102 and 103 are coupled to receive signals on input line 105, whereas the gate G of transistor 101 is coupled to receive signals from tristate control 107 and gate G of transistor 104 is coupled to receive the inverted signals from tristate control 107 via inverter 108. Note that inverter 108 inverts the signal from tristate control 107. Thus, a signal provided by tristate control 107 is provided at the gate G of transistor 101, and the complement of that signal is provided at the gate G of transistor 104.
If tristate control 107 provides a low signal, transistor 101 turns on, i.e. conducts, thereby transferring the high voltage from voltage source Vdd to node A. Inverter 108 inverts the low signal provided by tristate control 107, thereby providing a high signal to the gate of transistor 107. This high signal turns on transistor 104, thereby transferring the low voltage from ground to node B.
In this configuration, tristate inverter 100 functions as a conventional inverter. Specifically, a high signal on input line 105 turns on transistor 103 and turns off transistor 102. Because only transistor 103 is conducting, the low voltage on node B is transferred to the output line 106. Conversely, a low signal on input line 105 turns off transistor 103 and turns on transistor 102. Because only transistor 102 is conducting, the high voltage on node A is transferred to output line 106.
Tristate inverter 100 is placed in its high impedance state if tristate control 107 provides a high signal. Specifically, this high signal turns off both transistors 101 and 104. In this high impedance state, output line 106 provides no signal, irrespective of the signal provided on input line 105.
This configuration, however, results in an undesirable time delay during the time that the signal on input line 105 switches from high to low. As mentioned previously, assuming that tristate inverter 100 is in its inverter mode, i.e. tristate control 107 provides a low signal, node A exhibits a high voltage (typically Vdd). When the signal on input line 105 transitions from high to low, the voltage at node A also momentarily dips because of the capacitive coupling between input line 105 and node A (specifically the gate to drain capacitance C.sub.GD of transistor 101). The extent of the dip is determined by the size of transistor 101 (note that transistors 101 and 102 are conventionally identically sized). Specifically, the larger the size of transistor 101, the larger the capacitance C.sub.GD of transistor 101, thereby decreasing the current needed by transistor 102 to charge up output line 106. Thus, the dip in the voltage on node A creates an undesirable increase in the rise time of the signal on output line 106.
To compensate for this undesirable charging/discharging condition at node A, thereby decreasing the rise time of the signal on output line 106, transistor 102 is typically sized to be relatively large, i.e. commonly at least 100.mu. wide. However, this increase in the size of transistor 102 creates loading on output line 106, thereby once again increasing the time for the signal transition. Therefore, the prior art solution to the capacitive coupling problem creates a new problem that results in the same effect, i.e. an increased rise time of the signal on line 106.
Thus, a need arises for a tristate inverter which decreases the rise time of the signal on the output line of the inverter.